Msp430 Timer Block Diagram and Explain

Msp430 Timer Block Diagram and Explanation

In this post, we will discuss the msp430 timers block diagram and will explain it. Basically, the time I use is used for generating delay and Counting external events. And the timer Hardware in the microkernel is a counter driven by an internal or external clock signals counter is commonly incremented for accounting or decremented for downtown. On each clock pulse when the counter is the predefined set value, the timer can generate and send an interrupt to the CPU. 

Msp430 Timer Block Diagram

For counting the pulses timer have a counter instance with the size of 8-bit or 16-bit 8-bit. The timer is capable of holding value within 0 to 255 and the 16-bit timer is capable of holding value from 0 to 65535. The time also used to count external events and it is also used to generate PWM signal the signal shows the timer counter graphical representation.

The timers are available in the msp430 series controller are Timer A, Timer B, and timer D. 

Timer A is a 16-bit timer counter multiple captures or compares registers generate PWM and other complex waveforms and interrupts. 

Timer B in msp430. It is the same as Timer A but the improved version of pulse width modulation.

Timer D is the same as the Timer B with high Rising timings.

Before discussing timer A, the main features of timer A are: 

1. It is an asynchronous 16-bit timer or counter for operating modes.
2. selectable configurable clock Source up to seven configurable capture or compare Esther.
3. configurable output with PWM capability.
4. asynchronous input and output letching.

Msp430 Timer Block Diagram

Msp430 Timer Block Diagram and Explanation

Basically, timer A exists with a 16-bit timer counter and three captured compare registers. Timer A can support multiple captures Compares PWM outputs and interval timing. Interrupts may be generated from the timer or flow and from each of the capture compare register conditions the block diagram of the timer A is shown in the figure. 

In which there are two main hardware parts of timer A. The first one is the timer block. it has a 16-bit timer counter register. That one is TAR. 

TAR is controlled by a 16-bit register. That one is a timer control register. that t timer register is incremented or decremented with each Rising edge of the clock signals. The TAR can be read or written with software. TAR may be cleared by setting the TACLR bit setting. 

Secondly, TAR is also clears the clock divider and count direction for Uptown mode. The timer should be off condition before modifying its configuration and its operation. That timer clock has no output but a timer interrupt flag is raised when the counter returns to zero if timer interrupt enable bit is set, where is the clock source for timer TAR can be selected by TASSELX bit of TACTL register.